Draft RTL you can simulate
Give a spec. The intended workflow drafts the module, then shows lint and simulation results. You decide whether it is design.
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Give a spec. The intended workflow returns a module, lint notes, and a simulation log. An engineer reviews that evidence before treating it as design. Software coding and cited research briefs follow the same pattern.
Each one ends with something you can review: a simulation log, a diff, or a cited brief. None of these jobs is publicly available yet.
Give a spec. The intended workflow drafts the module, then shows lint and simulation results. You decide whether it is design.
Describe an issue. The intended workflow reads the repository, writes a change with tests, and hands you a summary of what ran.
Ask a research question. The intended workflow maps sources that support or contradict the finding, with citations you can check.
Written walkthrough of the intended loop: spec, draft, lint, simulation, correction. This is not a live Moolaii run and not a log from a public CLI. A passing testbench here means that testbench passed.
sync FIFO, 8-bit data, depth 4 clk, rst_n, wr_en, rd_en, din[7:0] dout[7:0], full, empty one clock domain simultaneous write+read must keep occupancy unchanged overflow and underflow must be ignored
always_ff @(posedge clk) begin if (wr_en) count <= count + 1'b1; if (rd_en) count <= count - 1'b1; // overwrites the write end
W1 fifo.sv:14 both wr_en and rd_en assign count
last assignment wins; occupancy is wrong on wr+rd
W2 fifo.sv:18 full/empty derived from count without
a wrap guard when wr+rd both firet=40 wr+rd count 3→2 expected 3 FAIL occupancy dropped on simultaneous wr+rd PASS 4 writes then empty after 4 reads (no overlap)
if (wr_en && rd_en && !empty && !full) count <= count; else if (wr_en && !full) count <= count + 1'b1; else if (rd_en && !empty) count <= count - 1'b1;
t=40 wr+rd count stays 3 PASS occupancy on simultaneous wr+rd PASS fill to full, drain to empty 4 writes, 4 reads, 2 overlap cycles
Limits: one clock domain, depth 4, no CDC, no synthesis, no timing closure, no formal proof. Questions about this example: [email protected].
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