Architecture
System requirements and microarchitecture.
Moolaii/Semiconductor
03 / SEMICONDUCTORIntelligence
meets silicon.
AI-assisted RTL and verification is the lead story. Architecture, lint, simulation, and synthesis notes are the intended loop. The FIFO walkthrough below is a written example, not a live product run.
MLI // RTLINTERNAL PROTOTYPE
RTL Design
Verilog / SystemVerilog engineering.
Verification
Simulation, UVM and formal verification.
Synthesis
Design readiness and optimization.
AI-Assisted Engineering
Intelligent workflows across chip development.
INTERACTIVE SYSTEM MAP
Select a stage to trace its inputs, engineering work, and feedback into the next cycle. Auto-playing — click any stage to take control.
Models turn engineering intent into actionable architecture.
Knowledge, specifications, and prior designs inform RTL generation, review, and implementation choices.
INPUTSSpecifications · prior IP · engineering knowledge
OUTPUTSDesign constraints · architecture options · RTL intent
NEXT CONNECTIONStructured intent feeds RTL Design →
RTL makes intelligence structurally precise.
SystemVerilog modules express the architecture while agents inspect interfaces, timing assumptions, and reusable IP.
INPUTSArchitecture · protocols · timing constraints
OUTPUTSSynthesizable RTL · assertions · test intent
NEXT CONNECTIONExecutable design enters Verification →
Verification converts behavior into evidence.
Simulation and coverage expose failures. A passing testbench is evidence for that testbench. It is not a claim of unrestricted correctness.
INPUTSRTL · assertions · test plans · requirements
OUTPUTSCoverage · counterexamples · testbench results
NEXT CONNECTIONEvidence qualifies Silicon Optimization →
Optimization closes the loop from silicon to intelligence.
Power, performance, area, and timing results can change the next architecture choice and the prompts or rules given to a later draft. That is not the same as retraining model weights.
INPUTSChecked RTL · PPA targets · technology data
OUTPUTSOptimized netlist · timing and power evidence
LOOP CONNECTIONMeasured results update architecture notes and agent guidance ↻
RTL workflow
One inspectable example.
Written walkthrough of the intended loop: spec, draft, lint, simulation, correction. This is not a live Moolaii run and not a log from a public CLI. A passing testbench here means that testbench passed.
- 01 · Spec
What to build
sync FIFO, 8-bit data, depth 4 clk, rst_n, wr_en, rd_en, din[7:0] dout[7:0], full, empty one clock domain simultaneous write+read must keep occupancy unchanged overflow and underflow must be ignored
- 02 · Draft
First occupancy logic
always_ff @(posedge clk) begin if (wr_en) count <= count + 1'b1; if (rd_en) count <= count - 1'b1; // overwrites the write end
- 03 · Lint
What a reviewer should catch
W1 fifo.sv:14 both wr_en and rd_en assign count last assignment wins; occupancy is wrong on wr+rd W2 fifo.sv:18 full/empty derived from count without a wrap guard when wr+rd both fire - 04 · Simulate
The overlap case fails
t=40 wr+rd count 3→2 expected 3 FAIL occupancy dropped on simultaneous wr+rd PASS 4 writes then empty after 4 reads (no overlap)
- 05 · Correct
Keep count on wr+rd
if (wr_en && rd_en && !empty && !full) count <= count; else if (wr_en && !full) count <= count + 1'b1; else if (rd_en && !empty) count <= count - 1'b1;
- 06 · Recheck
That testbench now passes
t=40 wr+rd count stays 3 PASS occupancy on simultaneous wr+rd PASS fill to full, drain to empty 4 writes, 4 reads, 2 overlap cycles
Limits: one clock domain, depth 4, no CDC, no synthesis, no timing closure, no formal proof. Questions about this example: [email protected].
WHERE AI HELPS
Engineering, accelerated.
Intended assistance at the points where chip teams lose the most time. Labels say what is built versus planned.
Spec to RTL
Turn interface specs and microarchitecture notes into draft SystemVerilog.
Internal prototypeLint & review
Catch structural issues, CDC risks and style drift before simulation.
PlannedCoverage closure
Suggest tests and assertions that target the holes in your coverage.
PlannedPPA exploration
Compare power, performance and area trade-offs across design options.
Planned05 / ENGINEERING FLOW
From idea to silicon.
01
Idea
Define intent02
Research
Connect knowledge03
Architecture
Model systems04
RTL
Describe hardware05
Verification
Prove behavior06
Silicon
Realize compute
PRIVATE PREVIEW · RTL FIRSTGive your ideas
some Moolai.
Join the waitlist, or write AlienX about partnership, research, or careers.