AI for RTL

Can language models read, write and reason about synthesizable RTL well enough to be trusted inside a real design flow?

Pair a draft with the same lint and simulation checks an engineer already runs. A passing testbench means that testbench passed. It is not a claim of unrestricted correctness.

This page states the question and the intended loop: draft RTL, then lint and simulate before anyone treats the module as design. The homepage FIFO walkthrough is a written example of that loop. No public task set, tool versions, or pass/fail rates are published here.

• A named task and testbench
• Model and tool versions
• Recorded failures and measured results